1. Field of the Invention
Embodiments of the present invention relate to a silicon carbide semiconductor device and a method of manufacturing a silicon carbide semiconductor device.
2. Description of the Related Art
A silicon carbide (SiC) semiconductor element has various advantages such as enabling the resistance of the element in an ON state to be reduced to one several hundredths and use under higher temperature environments (equal to or higher than 200 degrees C.) compared to a conventional semiconductor element that uses silicon (Si) as a material. This is due to properties of the material itself such as the bandgap of SiC being substantially threefold larger than that of Si and the breakdown electric field intensity thereof being ten-fold higher than that of Si.
Until now, Schottky barrier diodes and planar vertical metal oxide semiconductor field effect transistors (MOSFETs) have been produced (manufactured) as commercial SiC semiconductor elements and, in addition, a vertical MOSFET of a trench gate structure (hereinafter, referred to simply as “trench MOSFET”) has been proposed that aims to reduce element resistance by size reduction through increased channel density.
For a SiC trench MOSFET, two types of methods for forming a channel layer have been proposed, including an ion implantation method and an epitaxial growth method. When the channel layer is formed using ion implantation, a problem arises in that channel mobility is degraded due to crystal damage by the ion implantation and the roughness of the trench side wall surface after activation annealing.
On the other hand, when the channel layer is formed by epitaxial growth, although the channel mobility is improved, a problem arises in that a marker pattern for photolithography steps is deformed when the epitaxial growth (hereinafter, referred to simply as “epi growth”) is performed. The alignment precision is therefore degraded between before and after the epi growth and this imposes a significant restriction on the element structure and the method of manufacture.
For a SiC trench MOSFET, according to a conventional technique, a p-type layer is embedded at the bottom of a trench to protect an oxide film at the bottom of the trench (see, e.g., IEEE ELECTRON DEVICE LETTERS, 19, (1989) p. 487). FIG. 23 is a cross-sectional view of a structure of a conventional SiC trench device. FIG. 23 depicts a structure of a SiC trench device whose channel layer is formed by epi growth and that includes a structure in which a p-type layer is embedded at the trench bottom.
As depicted in FIG. 23, the conventional SiC trench device includes an n−-type drift layer 2, a p-type embedded layer 3, an n-type epitaxial layer 4, and a p-type epitaxial layer 5 provided on an n+-type silicon carbide substrate 1. A p+-type contact layer 6 and an n+-type source layer 7 are selectively provided in the p-type epitaxial layer 5. The conventional SiC trench device includes a source electrode 8, an interlayer insulating film 9, an electrode pad 10, a trench 11, a gate electrode 12, a gate oxide film 13, a drain electrode 14, and a rear electrode 15, and the p-type embedded layer 3 is embedded at the bottom of the trench 11.
FIGS. 24, 25, 26, 27, and 28 are cross-sectional views of the conventional SiC trench device during manufacture. When the channel layer is formed by epi growth, as depicted in FIG. 24, the n−-type drift layer 2 on the n+-type silicon carbide substrate 1 is first formed by epi growth. As depicted in FIG. 25, the p-type embedded layer 3 is formed in the n−-type drift layer 2 by ion implantation. Arrows in FIG. 25 indicate a region into which ions are implanted.
As depicted in FIG. 26, the n-type epitaxial layer 4 and the p-type epitaxial layer 5 to become the channel layer are formed on the n−-type drift layer 2 and the p-type embedded layer 3 by epi growth. As depicted in FIG. 27, the p+-type contact layer 6 and the n+-type source layer 7 are formed in the p-type epitaxial layer 5 by ion implantation. As depicted in FIG. 28, the trench 11 is formed by aligning a position thereof with a position of the p-type embedded layer 3. The source electrode 8, the interlayer insulating film 9, the electrode pad 10, the gate electrode 12, the gate oxide film 13, the drain electrode 14, and the rear electrode 15 are finally formed, and the SiC trench device depicted in FIG. 23 is thereby completed.
For the SiC trench device, according to a conventional technique, effects of step bunching are avoided and reduction of the dielectric breakdown and the life of the gate insulating film is suppressed by forming the trench using a <1-100> direction of the SiC semiconductor substrate as the longitudinal direction thereof (see, e.g., Japanese Laid-Open Patent Publication No. 2012-234908).